Pregled bibliografske jedinice broj: 987289
Interlocking schema based on GOOSE messages tested with IEC61850 protocol simulator
Interlocking schema based on GOOSE messages tested with IEC61850 protocol simulator // Proceedings Papers PAC World 2011. / Apostolov, Alex (ur.).
Dublin: PAC world magazine, 2011. str. 1-8 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), ostalo)
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Naslov
Interlocking schema based on GOOSE messages tested with IEC61850 protocol simulator
Autori
Pregrad, Goran ; Višić, Ivan
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), ostalo
Izvornik
Proceedings Papers PAC World 2011.
/ Apostolov, Alex - Dublin : PAC world magazine, 2011, 1-8
Skup
PAC world conference 2011.
Mjesto i datum
Dublin, Irska, 27.06.2011. - 30.06.2011
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
IEC61850, interlocking, GOOSE
Sažetak
Numerical relays joined with IEC61850 standard opened a great possibility to migrate interlocking logic in substations from hardwired to logic executed by numerical control relays. This introduced a big savings in time and materials required for hardwire solutions but it also created a need to develop new testing procedures and tools that will allow testing it and fully exploiting its advantages. Further more such a products are needed for all other functionalities which are migrated from wiring to IEC61850 communication based solutions. The study case for this article is refurbishment of the 400/220/110kV Mintia substation. A rather big SS of roughly forty bays needs to be refurbished bay per bay, while rest of it is in operation. With such a setting it was a challenge to prove functionality of interlocking system with only typical bays prepared for factory acceptance test. It was decided to use IEC61850 protocol simulator in order to make interlocking functional and available for testing and presenting to customer. As the configuration of substation is rather complicated, including transfer busbar and more sections on regular busbars, required logic was complicated. In order to test complete logic or interlocking schema it was necessary to simulate change of state for large number of elements.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika