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Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters


Bačmaga, Josip; Blečić, Raul; Barić, Adrijan
Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters // Proceedings of the IEEE International Conference on Industrial Technology (ICIT 2017)
Toronto: Institute of Electrical and Electronics Engineers (IEEE), 2017. str. 195-200 doi:10.1109/ICIT.2017.7913082 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


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Naslov
Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters

Autori
Bačmaga, Josip ; Blečić, Raul ; Barić, Adrijan

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the IEEE International Conference on Industrial Technology (ICIT 2017) / - Toronto : Institute of Electrical and Electronics Engineers (IEEE), 2017, 195-200

ISBN
978-1-5090-5320-9

Skup
18th Annual International Conference on Industrial Technology (ICIT 2017)

Mjesto i datum
Toronto, Kanada, 22.03.2017. - 25.03.2017

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
post-layout simulations ; SPI communication ; tapped delay-chain ; synchronous buck converter

Sažetak
A digital integrated circuit for sub-nanosecond dead-time adjustment is designed and its operation principle is described. The designed dead-time adjustment circuit (DTAC) generates two complementary control signals for the FET switches used in synchronous switching DC-DC converters. The control signals are generated from a PWM signal that is provided at the input of the DTAC. The circuit is based on a tapped delay-chain architecture and it is designed for the switching frequencies up to 10 MHz. The DTAC is designed in a 0.18-μm CMOS process. The impact of the process variations, ambient temperature and supply voltage on the achievable time-delay is investigated by the post-layout simulations. Additionally, the on- chip digital ‘slave’ circuit for serial communication is designed to allow programmability of the DTAC.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekti:
HRZZ IP-09-2014

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Raul Blečić (autor)

Avatar Url Josip Bačmaga (autor)

Avatar Url Adrijan Barić (autor)

Poveznice na cjeloviti tekst rada:

doi ieeexplore.ieee.org

Citiraj ovu publikaciju:

Bačmaga, Josip; Blečić, Raul; Barić, Adrijan
Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters // Proceedings of the IEEE International Conference on Industrial Technology (ICIT 2017)
Toronto: Institute of Electrical and Electronics Engineers (IEEE), 2017. str. 195-200 doi:10.1109/ICIT.2017.7913082 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Bačmaga, J., Blečić, R. & Barić, A. (2017) Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters. U: Proceedings of the IEEE International Conference on Industrial Technology (ICIT 2017) doi:10.1109/ICIT.2017.7913082.
@article{article, author = {Ba\v{c}maga, Josip and Ble\v{c}i\'{c}, Raul and Bari\'{c}, Adrijan}, year = {2017}, pages = {195-200}, DOI = {10.1109/ICIT.2017.7913082}, keywords = {post-layout simulations, SPI communication, tapped delay-chain, synchronous buck converter}, doi = {10.1109/ICIT.2017.7913082}, isbn = {978-1-5090-5320-9}, title = {Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters}, keyword = {post-layout simulations, SPI communication, tapped delay-chain, synchronous buck converter}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Toronto, Kanada} }
@article{article, author = {Ba\v{c}maga, Josip and Ble\v{c}i\'{c}, Raul and Bari\'{c}, Adrijan}, year = {2017}, pages = {195-200}, DOI = {10.1109/ICIT.2017.7913082}, keywords = {post-layout simulations, SPI communication, tapped delay-chain, synchronous buck converter}, doi = {10.1109/ICIT.2017.7913082}, isbn = {978-1-5090-5320-9}, title = {Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters}, keyword = {post-layout simulations, SPI communication, tapped delay-chain, synchronous buck converter}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Toronto, Kanada} }

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