Pregled bibliografske jedinice broj: 884918
Practical measurement of timing jitter contributed by a clock-and-data recovery circuit
Practical measurement of timing jitter contributed by a clock-and-data recovery circuit // IEEE Transactions on Circuits and Systems I : Regular Papers, 52 (2005), 1; 119-126 doi:10.1109/TCSI.2004.838260 (međunarodna recenzija, članak, znanstveni)
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Naslov
Practical measurement of timing jitter contributed by a clock-and-data recovery circuit
Autori
Pease, C. ; Babić, Dubravko I.
Izvornik
IEEE Transactions on Circuits and Systems I : Regular Papers (1057-7122) 52
(2005), 1;
119-126
Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni
Ključne riječi
Timing jitter, Clocks, Semiconductor device noise, Phase locked loops, Circuit noise, Semiconductor device measurement, Bit error rate, Frequency, Noise shaping, Communication standards
Sažetak
This paper describes a measurement of high- frequency jitter contributed by a clock-and- data recovery circuit. The contributed jitter is expressed with deterministic and random jitter terms and is given for a specific bit sequence. The measurement is illustrated on two multichannel CMOS serializer/deserializer chips applicable to 10-G Ethernet, 10-G Fibre Channel, and InfiniBand at per-channel rates of 2.5 and 3.125 GBaud.
Izvorni jezik
Engleski
Citiraj ovu publikaciju:
Časopis indeksira:
- Current Contents Connect (CCC)
- Web of Science Core Collection (WoSCC)
- SCI-EXP, SSCI i/ili A&HCI
