Naslov
Hierarchical Directory Controllers in the NUMAchine Multiprocessor

Autori
Alexander Grbic

Vrsta, podvrsta i kategorija rada
Ocjenski radovi, magistarski rad

Fakultet
Department of Electrical and Computer Engineering

Mjesto
Toronto, Kanada

Datum
24.09

Godina
1996

Stranica
133

Mentor
Siniša Srbljić - komentor s prof.dr.sc. Zvonko Vranešić

Ključne riječi
multiprocessor.

Sažetak
In multiprocessors, caching is an effective latency reducing technique. However, adding caches to a multiprocessor system also introduces the cache coherence problem. Many different solutions to this problem have been proposed and implemented. This work focuses on the design of hardware controllers that enforce cache coherence, enable non-coherent operations, uncached operations and special functions in the NUMAchine multiprocessor. The controller logic is functionally decomposed into simpler components which enables an efficient and flexible implementation in field-programmable devices (FPDs). The controllers have been built and tested to run at a clock rate of 50 MHz. This implementation of hardware cache coherence provides a good trade- off between cost, flexibility and performance, placing it between implementations using custom hardware and those using commodity parts.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA