Pregled bibliografske jedinice broj: 80885
High-Speed GaAs SCFL Digital Test Structures
High-Speed GaAs SCFL Digital Test Structures // The 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002) : Proceedings / Barić, Adrijan ; Magjarević, R. ; Pejčinović, B. ; Chrzanowska-Jeske, M. (ur.).
Piscataway (NJ): The Institut of Electrical and Electronic Engineers, 2002. str. 635-639 (poster, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
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Naslov
High-Speed GaAs SCFL Digital Test Structures
Autori
Marković, Hrvoje ; Marić, Nikica ; Čeperić, Vladimir ; Barić, Adrijan
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
The 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002) : Proceedings
/ Barić, Adrijan ; Magjarević, R. ; Pejčinović, B. ; Chrzanowska-Jeske, M. - Piscataway (NJ) : The Institut of Electrical and Electronic Engineers, 2002, 635-639
ISBN
0-7803-7596-3
Skup
IEEE International Conference on Electronics, Circuits and Systems (9 ; 2002)
Mjesto i datum
Dubrovnik, Hrvatska, 15.09.2002. - 18.09.2002
Vrsta sudjelovanja
Poster
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
GaAs; SCFL; high-speed; digital test structures
Sažetak
The work presented in this paper describes the simulations performed in order to evaluate expected performance of digital cells processed in 0.5-mm GaAs MESFET technology, before these cells are measured on-chip. A number of basic SCFL digital cells (buffer, OR, XOR, AND, D-flip-flop) is simulated, as well as various ring oscillator configurations and a programmable 2/3 divider. The cells used to generate pulse signals from the sine generator and the output cells used for measurements are also characterized. The simulations show that the operation up to 3 – ; ; 5 GHz may be achieved, which is consistent with what can be expected from the fT = 20 GHz 0.5-mm GaAs MESFET technology.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika