Naslov
Time Delay Testing in the Programmable Logic Circuit Design

Autori
Medved Rogina, Branka ; Skala, Karolj ; Vojnović, Božidar

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 20^th International Convention MIPRO'97. Conference on Microelectronics, Electronics and Electronic Technologies / Biljanović, Petar ; Skala, Karolj ; Ribarić, Slobodan ; Budin, Leo - Rijeka : Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 1997, 40-42

Skup
20^th International Convention MIPRO '97

Mjesto i datum
Opatija, Hrvatska, 19.05.1997. - 23.05.1997

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
time delay; bistable; pld; testing

Sažetak
The paper discusses timing delays which exist in Programmable Logic Devices (PLD) high-speed circuits applications. The statistical results of time delay measurements are applied in reliability analysis to predict the Mean Time Between Failure (MTBF) in PLD logic circuits design. It is shown that propagation (time) delay optimisation in design procedure has a marked effect on the PLD timing reliability characteristics. A good design approach would be to use macrofunction library structures rather than to create own cross-coupled implementations with primitives.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika, Informacijske i komunikacijske znanosti

POVEZANOST RADA