Naslov
JAGUAR: A Fully Pipelined VLSI Architecture for JPEG Image Compression Standard

Autori
Kovač, Mario ; Ranganathan, N.

Izvornik
Proceedings of the IEEE (0018-9219) 83 (1995), 2; 247-258

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
image compression; chip architecture; VLSI; JPEG; pipeline

Sažetak
In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard. The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024×1024 color images.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA