Pregled bibliografske jedinice broj: 703603
Performance-Occupation Trade-off Examination in Custom Processor Design
Performance-Occupation Trade-off Examination in Custom Processor Design // Proceedings of MIPRO 2014 37th International Convention / Biljanović, Petar (ur.).
Opatija: Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2014. str. 1258-1263 doi:10.1109/MIPRO.2014.6859719 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 703603 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Performance-Occupation Trade-off Examination in Custom Processor Design
Autori
Ivošević, Danko ; Frid, Nikolina
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of MIPRO 2014 37th International Convention
/ Biljanović, Petar - Opatija : Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2014, 1258-1263
Skup
MIPRO 2014 37th International Convention
Mjesto i datum
Opatija, Hrvatska, 26.05.2014. - 30.05.2014
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
Performance-area Trade-off ; Custom Processor Design ; FPGA Implementation ; Design Space Exploration
Sažetak
Trade-off between execution time and resource occupation is present in almost every digital system design process. Here we present such relation for FPGA-based custom processor design. Usually, the optimal tradeoff is governed by device sizing on all scales of the design, but for an FPGA device, as a predefined hardware platform, it is more focused on comparison of existing platforms organizations. The customization of processor architecture as a point of design performance improvement is usually focused on selection of parameter set that governs the most the design characteristics. In this paper, the focus is on processor architecture datapath with predefined design template and relationship of its structure to final FPGA implementation it maps to. For purpose of design evaluation at the ame time, the appropriate software flow is applied to explore the design space based on constraining of datapath functional units operation types. The data is collected throughout the whole design flow starting from input control and data flow characteristics of the application and ending with FPGA implementation data. The analysis of the design flow showed dependence of final implementation on datapath structure and its components complexities.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Projekti:
036-0362980-1929 - Oblikovanje okolina za ugradene sustave (Sruk, Vlado, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
