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Pregled bibliografske jedinice broj: 633634

Accurate timed RTOS model for transaction level modeling

Yonghyun Hwang; Schirner, Gunar; Abdi, Samar; Gajski, Daniel D.
Accurate timed RTOS model for transaction level modeling // Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Dresden, Njemačka: Institute of Electrical and Electronics Engineers (IEEE), 2010. str. 1333-1336 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)

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Naslov
Accurate timed RTOS model for transaction level modeling

Autori
Yonghyun Hwang ; Schirner, Gunar ; Abdi, Samar ; Gajski, Daniel D.

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 / - : Institute of Electrical and Electronics Engineers (IEEE), 2010, 1333-1336

Skup
Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010

Mjesto i datum
Dresden, Njemačka, 08.03.2010. - 12.03.2010

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
scheduling; transaction processing; JPEG encoder; RTOS behavior model; RTOS speciflc precharacterized overhead information; accurate timed RTOS model; cycle approximate estimation; dynamic scheduling; interprocess communication; multicore platform; system level design language; transaction level modeling; Application software; Context modeling; Delay estimation; Dynamic scheduling; Performance analysis; Scalability; Software performance; Switches; System-level design; Timing

Sažetak
In this paper, we present an accurate timed RTOS model within transaction level models (TLMs). Our RTOS model, implemented on top of system level design language (SLDL), incorporates two key features: RTOS behavior model and RTOS overhead model. The RTOS behavior model provides dynamic scheduling, inter-process communication (IPC), and external communication for timing annotated user applications. While the RTOS behavior model is running, all RTOS events, such as context switch and interrupt handling, are passed to RTOS over- head model to adopt the overhead during system execution. Our RTOS overhead model has processor- and RTOS-specific pre-characterized overhead information to provide cycle approximate estimation. We demonstrate the applicability of our model using a multi-core platform executing a JPEG encoder. Experimental results show that the proposed RTOS model provides the high accuracy, 7% off compared to on-board measurements while simulating at speeds close to the reference C code.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo



POVEZANOST RADA

Projekti:
036-0362980-1929 - Oblikovanje okolina za ugradene sustave (Sruk, Vlado, MZO ) ( CroRIS)

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Daniel Gajski (autor)

Poveznice na cjeloviti tekst rada:

Pristup cjelovitom tekstu rada

Citiraj ovu publikaciju:

Yonghyun Hwang; Schirner, Gunar; Abdi, Samar; Gajski, Daniel D.
Accurate timed RTOS model for transaction level modeling // Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Dresden, Njemačka: Institute of Electrical and Electronics Engineers (IEEE), 2010. str. 1333-1336 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Yonghyun Hwang, Schirner, G., Abdi, S. & Gajski, D. (2010) Accurate timed RTOS model for transaction level modeling. U: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010.
@article{article, author = {Schirner, Gunar and Abdi, Samar and Gajski, Daniel D.}, year = {2010}, pages = {1333-1336}, keywords = {scheduling, transaction processing, JPEG encoder, RTOS behavior model, RTOS speciflc precharacterized overhead information, accurate timed RTOS model, cycle approximate estimation, dynamic scheduling, interprocess communication, multicore platform, system level design language, transaction level modeling, Application software, Context modeling, Delay estimation, Dynamic scheduling, Performance analysis, Scalability, Software performance, Switches, System-level design, Timing}, title = {Accurate timed RTOS model for transaction level modeling}, keyword = {scheduling, transaction processing, JPEG encoder, RTOS behavior model, RTOS speciflc precharacterized overhead information, accurate timed RTOS model, cycle approximate estimation, dynamic scheduling, interprocess communication, multicore platform, system level design language, transaction level modeling, Application software, Context modeling, Delay estimation, Dynamic scheduling, Performance analysis, Scalability, Software performance, Switches, System-level design, Timing}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Dresden, Njema\v{c}ka} }
@article{article, author = {Schirner, Gunar and Abdi, Samar and Gajski, Daniel D.}, year = {2010}, pages = {1333-1336}, keywords = {scheduling, transaction processing, JPEG encoder, RTOS behavior model, RTOS speciflc precharacterized overhead information, accurate timed RTOS model, cycle approximate estimation, dynamic scheduling, interprocess communication, multicore platform, system level design language, transaction level modeling, Application software, Context modeling, Delay estimation, Dynamic scheduling, Performance analysis, Scalability, Software performance, Switches, System-level design, Timing}, title = {Accurate timed RTOS model for transaction level modeling}, keyword = {scheduling, transaction processing, JPEG encoder, RTOS behavior model, RTOS speciflc precharacterized overhead information, accurate timed RTOS model, cycle approximate estimation, dynamic scheduling, interprocess communication, multicore platform, system level design language, transaction level modeling, Application software, Context modeling, Delay estimation, Dynamic scheduling, Performance analysis, Scalability, Software performance, Switches, System-level design, Timing}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Dresden, Njema\v{c}ka} }

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