Pregled bibliografske jedinice broj: 60972
VHDL-Based Modeling of a Hard Real-Time Task Processor
VHDL-Based Modeling of a Hard Real-Time Task Processor // Proceedings of the IEEE International Symposium on Industrial Electronics ISIE'99, Volume 1 of 3 / Mihalič, Franc ; Harnik, Jože (ur.).
Piscataway (NJ): Institute of Electrical and Electronics Engineers (IEEE), 1999. str. 49-54 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
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Naslov
VHDL-Based Modeling of a Hard Real-Time Task Processor
Autori
Glavinić, Vlado ; Groš, Stjepan ; Colnarič, Matjaž
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the IEEE International Symposium on Industrial Electronics ISIE'99, Volume 1 of 3
/ Mihalič, Franc ; Harnik, Jože - Piscataway (NJ) : Institute of Electrical and Electronics Engineers (IEEE), 1999, 49-54
Skup
IEEE International Symposium on Industrial Electronics ISIE'99
Mjesto i datum
Bled, Slovenija, 12.07.1999. - 16.07.1999
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
hard real-time systems; CAD design tools; VHDL modeling; simulation; task processor
Sažetak
Hard real-time systems are increasingly used in various areas of human activities. They are often implemented by means of specialized solutions, mostly of a suitable hardware/software combination. A frequently adopted approach to the realization of the hardware part is based on ASIC, usually a general purpose processor which operates according to real-time constraints. This work describes the modeling of a processor for the hard real-time domain, which is structured as a collection of task processors being supervised by another one dedicated to the kernel functions. Specifically, the behavior of the task processors is modeled using VHDL and subsequently simulated and tested. The paper also addresses the modeling process by (i) evaluating available CAD tools, and (ii) determining the detailed requirements on the behavior of the task processor. The outcome of these steps influenced the modeling process as the tools used were of restricted functionality, and processor behavior enforced a particular decomposition, respectively. Because of a restricted VHDL subset available, it was necessary to model the task processor on the lowest level of behavioral abstraction. The task processor has been tested against selected test programs written in a corresponding assembly language specially developed for this purpose.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
