Naslov
Modeling and Simulation of a Hard Real-Time Processor

Autori
Glavinić, Vlado ; Groš, Stjepan ; Colnarič, Matjaž

Izvornik
Journal of Computing and Information Technology – CIT (1330-1136) 8 (2000), 3; 221-233

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
hard-real time; task processor; modeling and simulation; VHDL

Sažetak
Hard real-time systems are increasingly used in various areas of human activity justifying their implementation by means of specialized solutions, mostly of a suitable hardware/software combination. A frequently adopted approach to the realization of the hardware part is based on ASIC, usually a “general purpose” processor which operates according to real-time constraints. In this work the modeling of a processor for the hard real-time domain is described. It is structured as a collection of “task processors” being supervised by another one dedicated to the “kernel” functions. Specifically the behavior of the task processors is modeled using VHDL and subsequently simulated and tested. The paper also addresses the modeling process by determining the detailed requirements on the behavior of the task processor. The outcome of this step influenced the modeling process as the tools used were of restricted functionality and processor behavior enforced a particular decomposition. Because of a restricted VHDL subset available, it was necessary to model the task processor on the lowest level of behavioral abstraction. The task processor has been tested against chosen test programs written in an appropriate assembly language being specially developed for this purpose.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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