Pregled bibliografske jedinice broj: 525139
A Low-Power Fully Differential 9-Bit C-2C Cyclic ADC
A Low-Power Fully Differential 9-Bit C-2C Cyclic ADC // Proceedings of the 20th European Conference on Circuit Theory and Design / Wanhammar, Lars ; Dabrowski, Jerzy (ur.).
Linköping: Institute of Electrical and Electronics Engineers (IEEE), 2011. str. 597-600 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
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Naslov
A Low-Power Fully Differential 9-Bit C-2C Cyclic ADC
Autori
Bako, Niko ; Barić, Adrijan
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the 20th European Conference on Circuit Theory and Design
/ Wanhammar, Lars ; Dabrowski, Jerzy - Linköping : Institute of Electrical and Electronics Engineers (IEEE), 2011, 597-600
ISBN
978-1-4577-0616-5
Skup
The 20th European Conference on Circuit Theory and Design (ECCTD)
Mjesto i datum
Linköping, Švedska, 29.08.2011. - 31.08.2011
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
Low power; slew rate; RFID; C-2C; ADC
Sažetak
This paper describes a low-power fully differential cyclic ADC. It utilizes a 3-bit C-2C ladder to achieve 9-bit resolution. For the 9-bit resolution the 3-bit C-2C ladder occupies 64 times less area than a binary weighted capacitance array. The operational amplifier with the slew rate detection is used in order to increase the speed of the ADC. The simulated power consumption of the ADC is 33 µW@3.3 V at the sampling rate of 10 kS/s. The DNL and INL are both less than 0.53 LSB. The spurious-free dynamic range (SFDR) is 63 dB and the signal-tonoise and distortion ratio (SNDR) is 54.2 dB. The equivalent number of bits (ENOB) is 8.7.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Projekti:
036-0361621-1622 - Kvaliteta signala u integriranim sklopovima s mješovitim signalom (Barić, Adrijan, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb