Naslov
The Role of Post-Layout Verification in Microprocessor Design

Autori
Marković, Dubravko ; Ljuština, Dejan ; Cvijetić, Radenko ; Ivošević, Danko ; Rohtek, Oliver ; Rotim, Mario

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of MIPRO 2004 27th International Convention, MEET & HGS / Biljanović, Petar ; Skala, Karolj - Opatija : Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2004, 78-83

ISBN
953-233-001-1

Skup
MIPRO International Convention

Mjesto i datum
Opatija, Hrvatska, 24.05.2004. - 28.05.2004

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Microprocessor Design; Post-Layout Verification; LVS; DRC; Parasitic Extraction; Reduction; Reliability

Sažetak
Nanometer technology and high chip frequency place high demand on the EDA (Electronic Design Automation) tools to reliably and efficientlly find design problems in post-layout verification process. The only way to tackle designs with over billion transistors on a single chip is to use the knowledge and skill of highly experienced engineers in constant development and improvement of layout verification tools and methodologies. The purpose of this article is to present methodology and new challenges in layout verification and reliability checks of todays microprocessor layout designs.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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