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Pregled bibliografske jedinice broj: 51885

Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system


Ćosić, Krešimir; Kopriva, Ivica; Kostić, Todor; Slamić, Miroslav; Volarević, Marijo
Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system // Simulation practice and theory, 7 (1999), 2; 107-123 (međunarodna recenzija, članak, znanstveni)


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Naslov
Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system

Autori
Ćosić, Krešimir ; Kopriva, Ivica ; Kostić, Todor ; Slamić, Miroslav ; Volarević, Marijo

Izvornik
Simulation practice and theory (0928-4869) 7 (1999), 2; 107-123

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
Hardware in the loop simulation; semi-automatic guided missile systme; Digital signal processors; Parallel processing;

Sažetak
Hardware in the loop (HIL) simulation based on modern digital signal processors is a cost-effective technology for the design and evaluation of various sophisticated weapon and industrial systems. The semi-automatic command to line of sight (SACLOS) missile system is one example of a complex weapon system for which modernisation is a very complex process.The presented HIL simulation examples illustrate the essential importance of HIL simulation technology for cost-effective, non-destructive prototype development of such SACLOS systems. The Importance of the simulation kernel consisting of 4 TMS320C40 digital signal processors for efficient real-time simulation of the implemented SACLOS subsystem models is also emphasised in this paper.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekti:
036024

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Poveznice na cjeloviti tekst rada:

Pristup cjelovitom tekstu rada

Citiraj ovu publikaciju:

Ćosić, Krešimir; Kopriva, Ivica; Kostić, Todor; Slamić, Miroslav; Volarević, Marijo
Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system // Simulation practice and theory, 7 (1999), 2; 107-123 (međunarodna recenzija, članak, znanstveni)
Ćosić, K., Kopriva, I., Kostić, T., Slamić, M. & Volarević, M. (1999) Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system. Simulation practice and theory, 7 (2), 107-123.
@article{article, author = {\'{C}osi\'{c}, Kre\v{s}imir and Kopriva, Ivica and Kosti\'{c}, Todor and Slami\'{c}, Miroslav and Volarevi\'{c}, Marijo}, year = {1999}, pages = {107-123}, keywords = {Hardware in the loop simulation, semi-automatic guided missile systme, Digital signal processors, Parallel processing, }, journal = {Simulation practice and theory}, volume = {7}, number = {2}, issn = {0928-4869}, title = {Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system}, keyword = {Hardware in the loop simulation, semi-automatic guided missile systme, Digital signal processors, Parallel processing, } }
@article{article, author = {\'{C}osi\'{c}, Kre\v{s}imir and Kopriva, Ivica and Kosti\'{c}, Todor and Slami\'{c}, Miroslav and Volarevi\'{c}, Marijo}, year = {1999}, pages = {107-123}, keywords = {Hardware in the loop simulation, semi-automatic guided missile systme, Digital signal processors, Parallel processing, }, journal = {Simulation practice and theory}, volume = {7}, number = {2}, issn = {0928-4869}, title = {Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system}, keyword = {Hardware in the loop simulation, semi-automatic guided missile systme, Digital signal processors, Parallel processing, } }

Časopis indeksira:


  • Scopus


Uključenost u ostale bibliografske baze podataka::


  • The INSPEC Science Abstracts series
  • Current Content Electronics & Telecommunicatios





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