Pregled bibliografske jedinice broj: 492506
N-channel MOSFETs Fabricated on Self-Assembled SiGe Dots for Strain-Enhanced Mobility
N-channel MOSFETs Fabricated on Self-Assembled SiGe Dots for Strain-Enhanced Mobility // Proceedings of 13th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2010
Veldhoven, Nizozemska, 2010. str. 101-104 (poster, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 492506 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
N-channel MOSFETs Fabricated on Self-Assembled SiGe Dots for Strain-Enhanced Mobility
Autori
Jovanović, Vladimir ; Biasotto, Cleber ; Moers, Juergen ; Grützmacher, Detlev ; Zhang, Jianjun ; Hrauda, Nina ; Stoffel, Mathieu ; Pezzoli, Fabio ; Schmidt, Oliver G. ; Miglio, Leo ; Kosina, Hans ; Marzegalli, Anna ; Vastola, Guglielmo ; Mussler, Gregor ; Stangl, Julian ; Bauer, Guenther ; van der Cingel, Johan ; Bonera, Emiliano, Nanver, Lis K.
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of 13th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2010
/ - , 2010, 101-104
Skup
13th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2010
Mjesto i datum
Veldhoven, Nizozemska, 18.11.2010. - 19.11.2010
Vrsta sudjelovanja
Poster
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
CMOS; excimer-laser annealing (ELA); low-temperature gate stack; SiGe; strain-enhanced mobility; Stranski– Krastanow (S–K) growth mode; ultrashallow source/drain junctions
Sažetak
The dots of SiGe are grown in a Stranski-Krastanow mode in regular arrays and are used as sources of biaxial tensile strain in the Si layer grown over them. N-channel MOSFETs are fabricated with the channel region in the top Si layer over the SiGe dot in order to investigate mobility enhancement as a result of the strain imparted by the underlying SiGe dot. A dedicated fabrication process is developed with the maximum processing temperature after the growth of the dot structure of 400 ºC and ultrashallow source/drain junctions selfaligned to the gate formed by ion implantation and excimer-laser annealing. The comparison with the reference FETs processed in parallel shows the increase of drain current of up to 22.5 %.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Projekti:
036-0361566-1567 - Nanometarski elektronički elementi i sklopovske primjene (Suligoj, Tomislav, MZO ) ( CroRIS)
036-0982904-1642 - Sofisticirane poluvodičke strukture za komunikacijsku tehnologiju (Koričić, Marko, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
Profili:
Vladimir Jovanović
(autor)