Pregled bibliografske jedinice broj: 472410
Implementation of Division-Free Perspective-Correct Rendering Optimized for FPGA Devices
Implementation of Division-Free Perspective-Correct Rendering Optimized for FPGA Devices // Proceedings of MIPRO 2010 - 33rd International Convention on Information and Communication Technology, Electronics and Microelectronics
Opatija, Hrvatska, 2010. str. 203-208 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), stručni)
CROSBI ID: 472410 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Implementation of Division-Free Perspective-Correct Rendering Optimized for FPGA Devices
Autori
Šafaržik, Zdenka ; Gervais, Eugen ; Vučić, Mladen
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), stručni
Izvornik
Proceedings of MIPRO 2010 - 33rd International Convention on Information and Communication Technology, Electronics and Microelectronics
/ - , 2010, 203-208
Skup
33rd International Convention on Information and Communication Technology, Electronics and Microelectronics
Mjesto i datum
Opatija, Hrvatska, 24.05.2010. - 28.05.2010
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
perspective-correct rendering; division-free interpolation; midpoint algorithm; scanline; field programmable gate array; FPGA
Sažetak
Well-known algorithms for perspective-correct rendering of planar polygons in 3D graphic accelerators require per-pixel division. On the other hand, division is an expensive operation in the field programmable gate arrays (FPGAs) in the terms of silicon gates and clock cycles. Fortunately, efficient midpoint algorithms can be used to avoid division. This paper presents the implementation of such an algorithm in the renderer that is optimized for FPGA platform. The renderer implements the midpoint algorithm, which is based on separated computation of the integer parts and the fractional parts of the texture coordinates. The integer parts are used for texture fetching, whereas the fractional parts are used for texture filtering. The midpoint algorithm is embedded in a scanline algorithm. The pipeline architecture is used, resulting in a high clock frequency and high texturing fill-rate. The RTL model of the renderer is developed in VHDL, without the use of family-dependent macros. Therefore, the model is suitable for the reuse in various FPGA families.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Projekti:
036-0362214-2217 - Razvoj i implementacija učinkovitih postupaka za digitalnu obradu signala (Vučić, Mladen, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
Profili:
Mladen Vučić
(autor)