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Pregled bibliografske jedinice broj: 427391

Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices


Jovanović, Vladimir; Nanver, Lis K.; Suligoj, Tomislav; Poljak, Mirko
Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices // Proceedings of the 39th European Solid-State Device Research Conference / Tsoukalas, D. ; Dimoulas, A. (ur.).
Atena: Institute of Electrical and Electronics Engineers (IEEE), 2009. str. 241-244 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


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Naslov
Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices

Autori
Jovanović, Vladimir ; Nanver, Lis K. ; Suligoj, Tomislav ; Poljak, Mirko

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 39th European Solid-State Device Research Conference / Tsoukalas, D. ; Dimoulas, A. - Atena : Institute of Electrical and Electronics Engineers (IEEE), 2009, 241-244

ISBN
978-1-4244-4351-2

Skup
39th European Solid-State Device Research Conference

Mjesto i datum
Atena, Grčka, 14.09.2009. - 18.09.2009

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
FinFET; crystallographic etching; TMAH; ultra-narrow fin

Sažetak
FinFETs with 1 μ m tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekti:
036-0361566-1567 - Nanometarski elektronički elementi i sklopovske primjene (Suligoj, Tomislav, MZO ) ( CroRIS)
036-0982904-1642 - Sofisticirane poluvodičke strukture za komunikacijsku tehnologiju (Koričić, Marko, MZO ) ( CroRIS)

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Vladimir Jovanović (autor)

Avatar Url Tomislav Suligoj (autor)

Avatar Url Mirko Poljak (autor)


Citiraj ovu publikaciju:

Jovanović, Vladimir; Nanver, Lis K.; Suligoj, Tomislav; Poljak, Mirko
Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices // Proceedings of the 39th European Solid-State Device Research Conference / Tsoukalas, D. ; Dimoulas, A. (ur.).
Atena: Institute of Electrical and Electronics Engineers (IEEE), 2009. str. 241-244 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Jovanović, V., Nanver, L., Suligoj, T. & Poljak, M. (2009) Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices. U: Tsoukalas, D. & Dimoulas, A. (ur.)Proceedings of the 39th European Solid-State Device Research Conference.
@article{article, author = {Jovanovi\'{c}, Vladimir and Nanver, Lis K. and Suligoj, Tomislav and Poljak, Mirko}, year = {2009}, pages = {241-244}, keywords = {FinFET, crystallographic etching, TMAH, ultra-narrow fin}, isbn = {978-1-4244-4351-2}, title = {Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices}, keyword = {FinFET, crystallographic etching, TMAH, ultra-narrow fin}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Atena, Gr\v{c}ka} }
@article{article, author = {Jovanovi\'{c}, Vladimir and Nanver, Lis K. and Suligoj, Tomislav and Poljak, Mirko}, year = {2009}, pages = {241-244}, keywords = {FinFET, crystallographic etching, TMAH, ultra-narrow fin}, isbn = {978-1-4244-4351-2}, title = {Bulk-Si FinFET Technology for Ultra-High Aspect-Ratio Devices}, keyword = {FinFET, crystallographic etching, TMAH, ultra-narrow fin}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Atena, Gr\v{c}ka} }




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