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Optimization of Stress Distribution in Sub-45 nm CMOS Structures


Žilak, Josip; Knežević, Tihomir; Suligoj, Tomislav
Optimization of Stress Distribution in Sub-45 nm CMOS Structures // Proceedings of 45th International Conference on Microelectronics, Devices and Materials MIDEM 2009 / Topič M. ; Krč, J. ; Šorli, I. (ur.).
Ljubljana: Society for Microelectronics, Electronic Components and Materials (MIDEM), 2009. str. 85-90 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


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Naslov
Optimization of Stress Distribution in Sub-45 nm CMOS Structures

Autori
Žilak, Josip ; Knežević, Tihomir ; Suligoj, Tomislav

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of 45th International Conference on Microelectronics, Devices and Materials MIDEM 2009 / Topič M. ; Krč, J. ; Šorli, I. - Ljubljana : Society for Microelectronics, Electronic Components and Materials (MIDEM), 2009, 85-90

ISBN
978-961-91023-9-8

Skup
45th International Conference on Microelectronics, Devices and Materials MIDEM 2009

Mjesto i datum
Postojna, Slovenija, 09.09.2009. - 11.09.2009

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
CMOS; stress; shallow-trench isolation; gate spacers

Sažetak
The impact of stress on electrical characteristics for sub-45 nm CMOS is examined. Analyzed stress sources are STI, deposited oxide cover layer and gate spacers. Stress type and values from these sources are manipulated in order to get optimal influence on electrical characteristics. Optimal stress parameters for nMOS are 2 GPa of intrinsic stress in STI and deposited cover layer, while for pMOS are -2 GPa in STI and deposited cover layer and 2 GPa in spacers. With these optimal parameters maximum ION current increase for 25 nm channel length structure is 29.3 % for nMOS and 105.6 % for pMOS transistors. There is no large influence of stress on DIBL effect and S factor.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekti:
036-0361566-1567 - Nanometarski elektronički elementi i sklopovske primjene (Suligoj, Tomislav, MZO ) ( CroRIS)

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Tomislav Suligoj (autor)

Avatar Url Tihomir Knežević (autor)

Avatar Url Josip Žilak (autor)


Citiraj ovu publikaciju:

Žilak, Josip; Knežević, Tihomir; Suligoj, Tomislav
Optimization of Stress Distribution in Sub-45 nm CMOS Structures // Proceedings of 45th International Conference on Microelectronics, Devices and Materials MIDEM 2009 / Topič M. ; Krč, J. ; Šorli, I. (ur.).
Ljubljana: Society for Microelectronics, Electronic Components and Materials (MIDEM), 2009. str. 85-90 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Žilak, J., Knežević, T. & Suligoj, T. (2009) Optimization of Stress Distribution in Sub-45 nm CMOS Structures. U: Topič M., Krč, J. & Šorli, I. (ur.)Proceedings of 45th International Conference on Microelectronics, Devices and Materials MIDEM 2009.
@article{article, author = {\v{Z}ilak, Josip and Kne\v{z}evi\'{c}, Tihomir and Suligoj, Tomislav}, year = {2009}, pages = {85-90}, keywords = {CMOS, stress, shallow-trench isolation, gate spacers}, isbn = {978-961-91023-9-8}, title = {Optimization of Stress Distribution in Sub-45 nm CMOS Structures}, keyword = {CMOS, stress, shallow-trench isolation, gate spacers}, publisher = {Society for Microelectronics, Electronic Components and Materials (MIDEM)}, publisherplace = {Postojna, Slovenija} }
@article{article, author = {\v{Z}ilak, Josip and Kne\v{z}evi\'{c}, Tihomir and Suligoj, Tomislav}, year = {2009}, pages = {85-90}, keywords = {CMOS, stress, shallow-trench isolation, gate spacers}, isbn = {978-961-91023-9-8}, title = {Optimization of Stress Distribution in Sub-45 nm CMOS Structures}, keyword = {CMOS, stress, shallow-trench isolation, gate spacers}, publisher = {Society for Microelectronics, Electronic Components and Materials (MIDEM)}, publisherplace = {Postojna, Slovenija} }




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