Pregled bibliografske jedinice broj: 422598
1.9 nm Wide Ultra-High Aspect-Ratio Bulk-Si FinFETs
1.9 nm Wide Ultra-High Aspect-Ratio Bulk-Si FinFETs // Device Research Conference - Conference Digest / Koester, S. ; Gundlach, D. ; Fay, P. (ur.).
State College (PA), Sjedinjene Američke Države: Institute of Electrical and Electronics Engineers (IEEE), 2009. str. 261-262 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 422598 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
1.9 nm Wide Ultra-High Aspect-Ratio Bulk-Si FinFETs
Autori
Jovanović, Vladimir ; Poljak, Mirko ; Suligoj, Tomislav ; Civale, Yann ; Nanver, Lis K.
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Device Research Conference - Conference Digest
/ Koester, S. ; Gundlach, D. ; Fay, P. - : Institute of Electrical and Electronics Engineers (IEEE), 2009, 261-262
Skup
Device Research Conference
Mjesto i datum
State College (PA), Sjedinjene Američke Države, 22.06.2009. - 24.06.2009
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
bulk; body-tied; FinFET; ultra-high aspect-ratio
Sažetak
FinFETs are foreseen as a solution for the suppression of short-channel effects (SCE) from the 22 nm node onwards because of their superior electrostatic integrity achieved with a fabrication technique that is similar to bulk CMOS processes. To keep SCEs under control the width of the etched fins must be reduced as the gate-length is scaled down. The fin-height is typically reduced as well to keep the same aspect ratio between the fin-height and fin-width which allows the same fin-etching processes to be used also for smaller devices. This work focuses on FinFETs with high aspect-ratio and thus a wide MOSFET channels in each fin, which translates into higher device density per chip area and more efficient use of the silicon real-estate. Moreover, in analog applications where multi-fin devices are required for wider transistors, a small number of taller fins is preferable to a large number of shorter fins in terms of gate resistance and gate capacitance which improves high-frequency performance. The fabrication process is designed to keep the fin-width in the 10 nm range while at the same time tall fins are etched.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Projekti:
036-0361566-1567 - Nanometarski elektronički elementi i sklopovske primjene (Suligoj, Tomislav, MZO ) ( CroRIS)
036-0982904-1642 - Sofisticirane poluvodičke strukture za komunikacijsku tehnologiju (Koričić, Marko, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb