Pregled bibliografske jedinice broj: 410778
Custom Processor Core Construction from C Code
Custom Processor Core Construction from C Code // Proceedings of Symposium on Application Specific Processors, 2008. SASP 2008.
Anaheim (CA), 2008. str. 1-6 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 410778 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Custom Processor Core Construction from C Code
Autori
Trajkovic, Jelena ; Gajski, Daniel
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of Symposium on Application Specific Processors, 2008. SASP 2008.
/ - Anaheim (CA), 2008, 1-6
ISBN
978-1-4244-2333-0
Skup
Symposium on Application Specific Processors, 2008. SASP 2008.
Mjesto i datum
Anaheim (CA), Sjedinjene Američke Države, 08.06.2008. - 09.06.2008
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
C code; application specific processor cores; custom processor core construction; interactive data path refinement algorithm; parallelism
Sažetak
In this paper we present a method for construction of application specific processor cores from a given C code. Our approach consists of three phases. We start by quantifying the properties of the C code in terms of operation types, available parallelism and other metrics. We then create an initial data path to exploit the available parallelism. We then apply designer guided constraints to an interactive data path refinement algorithm that attempts to reduce the number of the most expensive components while meeting the constraints. Our experimental results show that our technique scales very well with the size of the C code. We demonstrate the efficiency of our technique on wide range of applications, from standard academic benchmarks to industrial size examples like the MP3 decoder. Each processor core was constructed and refined in under a minute, allowing the designer to explore several different configurations in much less time than needed for manual design. On average, the refined core have only 23% latency overhead, twice as many block RAMs and 36% fewer slices compared to the respective manual designs.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Projekti:
036-0362980-1929 - Oblikovanje okolina za ugradene sustave (Sruk, Vlado, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb