Pregled bibliografske jedinice broj: 378421
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters // IEE Proceedings E (Computers and Digital Techniques), 136 (1989), 450-455 (podatak o recenziji nije dostupan, članak, znanstveni)
CROSBI ID: 378421 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters
Autori
Švedek, Tomislav ; V.Ivančić
Izvornik
IEE Proceedings E (Computers and Digital Techniques) (1350-2387) 136
(1989);
450-455
Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni
Ključne riječi
ASIC; test sequence; testability; asynchronous counters
Sažetak
The parallel/serial test procedure for application-specific integrated circuit (ASIC) logic surrounding embedded asynchronous counters is proposed, which increases counter controllability and observability and reduces test sequence length. Optimisation of counter partitioning and test sequence generation is carried out with the CAD program COUNTESS. For optimal partitioning COUNTESS calculates both the test hardware overhead and the minimum number of test cycles
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
