Pregled bibliografske jedinice broj: 364605
Vertical Silicon-on-Nothing FET: Subthreshold Slope Calculation Using Compact Capacitance Model
Vertical Silicon-on-Nothing FET: Subthreshold Slope Calculation Using Compact Capacitance Model // Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials, 38 (2008), 1; 1-4 (međunarodna recenzija, članak, znanstveni)
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Naslov
Vertical Silicon-on-Nothing FET: Subthreshold Slope Calculation Using Compact Capacitance Model
Autori
Sviličić, Boris ; Jovanović, Vladimir ; Suligoj, Tomislav
Izvornik
Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials (0352-9045) 38
(2008), 1;
1-4
Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni
Ključne riječi
Silicon-on-Nothing ; fully-depleted MOSFET ; vertical SONFET ; subthreshold slope ; compact model
Sažetak
The subthreshold slope model of the Vertical Silicon-on-Nothing FET, extracted from the compact capacitance model, has been developed. For short-channel effects modeling the voltage-doping transformation is used. The analytical model is verified by comparison to the two-dimensional numerical device simulator, MEDICI, over a wide range of different device structures. Good agreement is obtained for channel lengths down to 50 nm.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Projekti:
036-0361566-1567 - Nanometarski elektronički elementi i sklopovske primjene (Suligoj, Tomislav, MZO ) ( CroRIS)
036-0982904-1642 - Sofisticirane poluvodičke strukture za komunikacijsku tehnologiju (Koričić, Marko, MZO ) ( CroRIS)
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb,
Pomorski fakultet, Rijeka
Citiraj ovu publikaciju:
Časopis indeksira:
- Web of Science Core Collection (WoSCC)
- Science Citation Index Expanded (SCI-EXP)
- SCI-EXP, SSCI i/ili A&HCI
- Scopus
Uključenost u ostale bibliografske baze podataka::
- INSPEC
- SCI Expanded
