Naslov
Vertical Silicon-on-Nothing FET: Capacitance-Voltage Compact Modeling

Autori
Sviličić, Boris ; Jovanović, Vladimir ; Suligoj, Tomislav

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 30th International Convention MIPRO 2007 / P. Biljanović, K. Skala - Rijeka : Studio Hofbauer, 2007, 84-88

ISBN
978-953-233-032-8

Skup
30th International Convention MIPRO

Mjesto i datum
Opatija, Hrvatska, 21.05.2007. - 25.05.2007

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
silicon-on-nothing (SON); vertical SONFET; fully depleted; compact modeling

Sažetak
The capacitance-voltage characteristics of Vertical Fully-Depleted Silicon-On-Nothing FET (VFD SONFET) is modeled, taking into account all of the intrinsic and extrinsic capacitance components. The equivalent circuit for the accumulation, depletion and inversion regions is introduced. The analytical model has been verified by comparing the calculated characteristics with the two-dimensional numerical device simulator results obtained by Medici. The effects that are specific to VFD SONFET are identified and explained by the introduced model. The drop of the gate capacitance in the accumulation region is explained by the lack of substrate underneath the transistor channel and the dominance of the buried oxide capacitance over the gate oxide capacitance. The further decrease of the capacitance in the accumulation region is due to the neutral source and drain depletion as the gate voltage is more negative, because of the large overlap capacitances. The developed model fits the Medici results in all of the operation regions.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika

POVEZANOST RADA