Naslov
FPGA-friendly code compression for horizontal microcoded custom IPs

Autori
Gorjiara, Bita ; Gajski, Daniel D.

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays / DeHon, André ; Hutton, Mike - New York (NY) : The Association for Computing Machinery (ACM), 2007, 108-115

ISBN
978-1-59593-600-4

Skup
International Symposium on Field Programmable Gate Arrays

Mjesto i datum
Monterey (CA), Sjedinjene Američke Države, 18.02.2007. - 20.02.2007

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Microcoded Architectures; No-Instruction-Set Computer; Memory optimization; Dictionary-based compression; FPGA

Sažetak
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meeting timing constraints of automatically generated IPs is often a challenging and time-consuming task that must be repeated every time the specification is modified. To address this issue, a new generation of IP-design technologies that is capable of generating custom datapaths as well as programming an existing one is developed. These technologies are often based on Horizontal Microcoded Architectures. Large code size is a well-know problem in HMAs, and is referred to as "code bloating" problem.In this paper, we study the code size of one of the new HMA-based technologies called NISC. We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionary-based code compression techniques to reduce the code size. Our compression algorithm leverages the knowledge of "don't care" values in the control words to better compress the content of dictionary memories. Our experiments show that by selecting proper memory architectures the code size of NISC can be reduced by 70% (i.e. 3.3 times) at cost of only 9% performance degradation. We also show that some code compression techniques may increase number of utilized block RAMs in FPGA-based implementations. To address this issue, we propose combining dictionaries and implementing them using embedded dual-port memories.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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