Naslov
Problems in PLD Implementation of All-digital DLL

Autori
Matić, Tomislav ; Švedek, Tomislav ; Herceg, Marijan

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
2008 3rd International Symposium on Communications, Control and Signal Processing (ISCCSP 2008) / Debono, Carl J. ; Gabbouj, Moncef - : Institute of Electrical and Electronics Engineers (IEEE), 2008, 1107-1110

ISBN
978-1-4244-1688-2

Skup
2008 3rd International Symposium on Communications, Control and Signal Processing (ISCCSP 2008)

Mjesto i datum
San Ġiljan, Malta, 12.03.2008. - 14.03.2008

Vrsta sudjelovanja
Poster

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Programmable Logic Device (PLD); All-digital DLL; Digital Controlled Delay Line

Sažetak
Problems encountered in the implementation of an all-digital delay-locked loop (DLL) in programmable logic devices (PLD) are presented. All parts of a DLL are only created by discrete digital elements. A digital controlled delay line (DCDL) consists of digital controlled delay elements (DCDE) realized by a number of LCELLs (basic delay elements in ALTERA's PLD). An analog charge pump (CP) and a loop filter (LF) in the proposed circuit are replaced with a 3-bit UP/DOWN/HOLD counter. The proposed DLL is implemented and tested in the ALTERA PLD chip EPM7128SLI10.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika

POVEZANOST RADA