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Pregled bibliografske jedinice broj: 325301

Generic netlist representation for system and PE level design exploration


Chandraiah, Pramod; Reshadi, Mehrdad; Gajski, Daniel; Gorjiara, Bita
Generic netlist representation for system and PE level design exploration // Proceedings of the 4th international conference Hardware/software codesign and system synthesis, 2006. CODES+ISSS '06.
Seoul, Republika Koreja, 2006. str. 282-287 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


CROSBI ID: 325301 Za ispravke kontaktirajte CROSBI podršku putem web obrasca

Naslov
Generic netlist representation for system and PE level design exploration

Autori
Chandraiah, Pramod ; Reshadi, Mehrdad ; Gajski, Daniel ; Gorjiara, Bita

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 4th international conference Hardware/software codesign and system synthesis, 2006. CODES+ISSS '06. / - , 2006, 282-287

Skup
International conference Hardware/software codesign and system synthesis

Mjesto i datum
Seoul, Republika Koreja, 22.10.2006. - 25.10.2006

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
GNR; NISC; application-specific processor; architecture description language; modeling; synthesis; system design

Sažetak
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration).In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo



POVEZANOST RADA


Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Daniel Gajski (autor)


Citiraj ovu publikaciju:

Chandraiah, Pramod; Reshadi, Mehrdad; Gajski, Daniel; Gorjiara, Bita
Generic netlist representation for system and PE level design exploration // Proceedings of the 4th international conference Hardware/software codesign and system synthesis, 2006. CODES+ISSS '06.
Seoul, Republika Koreja, 2006. str. 282-287 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Chandraiah, P., Reshadi, M., Gajski, D. & Gorjiara, B. (2006) Generic netlist representation for system and PE level design exploration. U: Proceedings of the 4th international conference Hardware/software codesign and system synthesis, 2006. CODES+ISSS '06..
@article{article, author = {Chandraiah, Pramod and Reshadi, Mehrdad and Gajski, Daniel and Gorjiara, Bita}, year = {2006}, pages = {282-287}, keywords = {GNR, NISC, application-specific processor, architecture description language, modeling, synthesis, system design}, title = {Generic netlist representation for system and PE level design exploration}, keyword = {GNR, NISC, application-specific processor, architecture description language, modeling, synthesis, system design}, publisherplace = {Seoul, Republika Koreja} }
@article{article, author = {Chandraiah, Pramod and Reshadi, Mehrdad and Gajski, Daniel and Gorjiara, Bita}, year = {2006}, pages = {282-287}, keywords = {GNR, NISC, application-specific processor, architecture description language, modeling, synthesis, system design}, title = {Generic netlist representation for system and PE level design exploration}, keyword = {GNR, NISC, application-specific processor, architecture description language, modeling, synthesis, system design}, publisherplace = {Seoul, Republika Koreja} }




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