Naslov
Features supporting sytem-level specification in HDLs

Autori
Narayan, S., Gajski, D.D.

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of European Design Automation Conference / - , 1993, 540-545

Skup
European Design Automation Conference

Mjesto i datum
Hamburg, Njemačka, 20.09.1993. - 24.09.1993

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
embedded systems; HDL; system level design

Sažetak
As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. In this paper, issues related to the specification of embedded systems are discussed. We compare VHDL with five other specific languages: HardwareC, SDL (Speficication and Description Lanaguage), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system level are highlighted. We conclude by presenting a list of features which are desirable in a language to be used for specifying systems.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA