Pregled bibliografske jedinice broj: 324634
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms // Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
San Diego (CA), 2007. str. 143-145 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
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Naslov
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms
Autori
Viskic I., Abdi S., Gajski D. D.
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
/ - San Diego (CA), 2007, 143-145
Skup
ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Mjesto i datum
San Diego (CA), Sjedinjene Američke Države, 13.06.2007. - 15.06.2007
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
Automatic synthesis; Custom communication SW; MPSoC; On-chip communication; Pin/cycle accurate models; Platform based design; System level design; Transaction level models
Sažetak
This paper addresses the problem of long design cycle of MPSoCs communication SW with automatic synthesis. The tool we propose takes as input a transaction level model (TLM) of MPSoC communication and outputs pin and cycle-accurate (PCA) bus drivers that can be linked to the synthesizable PCA model (PCAM). The TL communication is simple since TLM channels abstract away protocol details. PCAM communication, in turn, includes explicit definitions for each signal and pin. However, in most cases the TLMs are not suitable for implementation since they do not reflect the MPSoC platform. Usually the designers simulate (fast) TLMs, then manually implement PCA communication. Our communication SW synthesis transforms TL send and receive functions into platform specific PCAM bus drivers which can be automatically downloaded to the FPGA board. The presented results demonstrate the significant productivity gain achieved with our tool, with no great cost to either code size or system performance.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
Profili:
Daniel Gajski
(autor)