Pregled bibliografske jedinice broj: 295018
Timing models for high-level synthesis
Timing models for high-level synthesis // Proceedings of the European Design Automation Conference
Hamburg, Njemačka: Institute of Electrical and Electronics Engineers (IEEE), 1992. str. 60-65 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 295018 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Timing models for high-level synthesis
Autori
Chaiyakul, Viraphol ; Wu, Allen C.-H. ; Gajski, Daniel D.
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the European Design Automation Conference
/ - : Institute of Electrical and Electronics Engineers (IEEE), 1992, 60-65
ISBN
0-818-62780-8
Skup
European Design Automation Conference
Mjesto i datum
Hamburg, Njemačka, 07.09.1992. - 10.09.1992
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
clock estimation; high-level synthesis
Sažetak
A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
Profili:
Daniel Gajski
(autor)
