Pregled bibliografske jedinice broj: 295017
Accurate Layout Area and Delay Modeling for System-Level Design
Accurate Layout Area and Delay Modeling for System-Level Design // Procedings of International Conference on Computer-Aided Design
Santa Clara (CA), Sjedinjene Američke Države: Institute of Electrical and Electronics Engineers (IEEE), 1992. str. 355-361 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 295017 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Accurate Layout Area and Delay Modeling for System-Level Design
Autori
Ramachandran, C. ; Kurdahi, F. J. ; Gajski, D. D., ; Chaiyakul, V. ; Wu, A. C-H. ;
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Procedings of International Conference on Computer-Aided Design
/ - : Institute of Electrical and Electronics Engineers (IEEE), 1992, 355-361
ISBN
0-818-63010-8
Skup
International Conference on Computer-Aided Design
Mjesto i datum
Santa Clara (CA), Sjedinjene Američke Države, 08.11.1992. - 12.11.1992
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
Layout area; RT level design
Sažetak
The problem of estimating design quality measures to accurately reflect design tradeoffs and efficiently explore the design space is discussed. Specifically, interest is centered on predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, a layout model which accurately and efficiently accounts for the effects of wiring and floorplanning on the area and performance layout of RT level designs is proposed. Benchmarking has shown that this model is quite accurate
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
Profili:
Daniel Gajski
(autor)
