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Pregled bibliografske jedinice broj: 294967

Clock Optimization for High-Performance Pipelined Design


Juan, Hsiao-Ping; Gajski, Daniel D.; Bakshi, Smita
Clock Optimization for High-Performance Pipelined Design // European Design Automation Conference - Proceedings
Ženeva, Švicarska, 1996. str. 330-335 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


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Naslov
Clock Optimization for High-Performance Pipelined Design

Autori
Juan, Hsiao-Ping ; Gajski, Daniel D. ; Bakshi, Smita

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
European Design Automation Conference - Proceedings / - , 1996, 330-335

Skup
European Design Automation Conference

Mjesto i datum
Ženeva, Švicarska, 16.09.1996. - 20.09.1996

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Adders; Algorithms; Computer simulation; Constraint theory; Estimation; Graph theory; Multiplying circuits; Optimization

Sažetak
In order to reduce the design cost of pipelined systems, resources may be shared by operations within and across different pipe stages. In order to maximize resource sharing, a crucial decision is the selection of a clock period, since a bad choice can adversely affect the performance and cost of the design. We present an algorithm to select a clock period that attempts to minimize design area while satisfying a given throughput constraint. Experimental results on several examples demonstrate the quality of our selection algorithm and the benefit of allowing resource sharing across pipe stages.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo



POVEZANOST RADA


Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Daniel Gajski (autor)


Citiraj ovu publikaciju:

Juan, Hsiao-Ping; Gajski, Daniel D.; Bakshi, Smita
Clock Optimization for High-Performance Pipelined Design // European Design Automation Conference - Proceedings
Ženeva, Švicarska, 1996. str. 330-335 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Juan, H., Gajski, D. & Bakshi, S. (1996) Clock Optimization for High-Performance Pipelined Design. U: European Design Automation Conference - Proceedings.
@article{article, author = {Juan, Hsiao-Ping and Gajski, Daniel D. and Bakshi, Smita}, year = {1996}, pages = {330-335}, keywords = {Adders, Algorithms, Computer simulation, Constraint theory, Estimation, Graph theory, Multiplying circuits, Optimization}, title = {Clock Optimization for High-Performance Pipelined Design}, keyword = {Adders, Algorithms, Computer simulation, Constraint theory, Estimation, Graph theory, Multiplying circuits, Optimization}, publisherplace = {\v{Z}eneva, \v{S}vicarska} }
@article{article, author = {Juan, Hsiao-Ping and Gajski, Daniel D. and Bakshi, Smita}, year = {1996}, pages = {330-335}, keywords = {Adders, Algorithms, Computer simulation, Constraint theory, Estimation, Graph theory, Multiplying circuits, Optimization}, title = {Clock Optimization for High-Performance Pipelined Design}, keyword = {Adders, Algorithms, Computer simulation, Constraint theory, Estimation, Graph theory, Multiplying circuits, Optimization}, publisherplace = {\v{Z}eneva, \v{S}vicarska} }




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