Pregled bibliografske jedinice broj: 294956
RT Level Power Analysis
RT Level Power Analysis // Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Chiba, Japan, 1997. str. 517-522 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 294956 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
RT Level Power Analysis
Autori
Zhu, Jianwen ; Agrawal, Poonam ; Gajski, Daniel D.
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
/ - , 1997, 517-522
Skup
Asia and South Pacific Design Automation Conference, ASP-DAC
Mjesto i datum
Chiba, Japan, 28.01.1997. - 31.01.1997
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
Capacitance; Energy dissipation; Estimation; Integrated circuit testing; Semiconductor device models
Sažetak
Elevating power estimation to architectural and behavioral level is essential for design exploration beyond logic level. In contrast with purely statistical approach, an analytical model is presented to estimate the power consumption in datapath and controller for a given RT level design. Experimental result shows that order of magnitude speed-up over low level tools as well as satisfactory accuracy can be achieved. This work can also serve as the basis for behavioral level estimation tool.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
Profili:
Daniel Gajski
(autor)
