Naslov
Model validation for mapping specification behaviors to processing elements

Autori
S. Abdi ; Gajski, D.D.,

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT / - , 2004, 101-106

ISBN
0-7803-8714-7

Skup
IEEE International High-Level Design Validation and Test Workshop, HLDVT

Mjesto i datum
Sonoma (CA), Sjedinjene Američke Države, 12.11.2004. - 14.11.2004

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
functional validation; functional equivalence; system level models

Sažetak
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for checking functional equivalence of system level models, before and after the distribution of behaviors in the specification over components in the platform architecture. We derive a control flow graph from models written in system level design languages (SLDLs) and reduce it to a normal form representation using well defined rules. Two models having identical normal form are shown to be functionally equivalent. An equivalence checker based on the above concept is used to automatically check if the architecture level model is functionally equivalent to the specification model. As a result, the models generated for various mapping decisions do not have to be reverified using costly simulations.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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