Naslov
An Ultra-Fast Instruction Set Simulator

Autori
Zhu, J. ; Gajski, Danijel

Izvornik
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1063-8210) 10 (2002), 3; 363-373

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
computing; high performance; logic simulation; system level

Sažetak
In this paper, we present new techniques which further improve the static compilation-based instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such utilization is achieved by defining a low-level code-generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code-generation interface. We are able to perform the simulation at a speed of up to 102 millions of simulated instructions per second (MIPS) on a 270 MHz Ultra-5 workstation. This result is only on average 1.6 times slower than the native execution on the host machine, the fastest to the best of our knowledge.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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