Naslov
Power Routing in Channelless Floorplan Layouts

Autori
Lursinsap, C. ; Gajski, Danijel

Izvornik
Integration - the VLSI Journal (0167-9260) 8 (1989), 3; 249-268

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
silicon compiler; layout architecture; power line

Sažetak
In a top-down design approach, a layout is decomposed into cells connected by abutment. The active cells contain transistors and interconnections, while passive cells are routing cells. This paper discusses the power routing of all active cells so that the total wire length and number of vias are minimized. The problem is considered as a special case of a Steiner tree, called a minimum power tree (MPT). We give a power routing algorithm and prove it to be optimal.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA