Naslov
A Technique for Pull-up Transistor Folding

Autori
Lursinsap, C. ; Gajski, Danijel

Izvornik
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems (0278-0070) 7 (1988), 8; 887-896

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
cellular arrays; circuit layout CAD; integrated logic circuits; logic CAD; PLA; area improvement; constraint limiting multiple folding; layout architecture; layouts; metal layer; optimization algorithms; programmable logic array

Sažetak
The authors consider the constraint limiting multiple folding in programmable logic array (PLA) layouts imposed by the layout architecture which positions pull-up transistors on the boundary of the cell and uses another metal layer to connect pull-ups to terms inside the PLA. The general PLA architecture supports only input- and output-port folding by sharing them in either the same column or the same row. Term folding is allowed only with drastic changes in the layout architecture. Folding optimization algorithms, generally, have not considered a pull-up transistor placement as a constraint. A layout architecture is introduced and a technique for pull-up transistor folding based on a weighted-graph model is presented. The architecture supports also both I/O and term foldings. In comparison with other architectures the described architecture allows significant area improvement

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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