Naslov
Layout Placement for Sliced Architecture

Autori
Larmore, L. L. ; Gajski, Danijel ; Wu, A. C-H.

Izvornik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (0278-0070) 2 (1992), 1; 102-114

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
CMOS technology; area minimization; interleaved folding; layout area optimisation; layout placement; sliced architecture; unrestricted folding

Sažetak
The authors define a new, sliced layout architecture for compilation of arbitrary schematics (netlists) into layout for CMOS technology. This sliced architecture uses over-the-cell routing on the second metal layer. The authors define three different architectures with simple folding, interleaved folding, and unrestricted folding and give algorithms for optimizing the layout area for several variants of the selected architecture. A proof demonstrating that the architecture with interleaved folding is as good as the architecture with unrestricted folding with respect to area minimization of the total layout is given. The authors also present results of random benchmarks as well as several real benchmarks.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA