Pregled bibliografske jedinice broj: 286698
Design and Optimization of Self-Biased Complementary Folded Cascode
Design and Optimization of Self-Biased Complementary Folded Cascode // Proceedings of the 13th IEEE Mediterranean Electrotechnical Conference (MELECON 2006)
Málaga: Institute of Electrical and Electronics Engineers (IEEE), 2006. str. 145-148 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 286698 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Design and Optimization of Self-Biased Complementary Folded Cascode
Autori
Čeperić, Vladimir ; Butković, Željko ; Barić, Adrijan
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the 13th IEEE Mediterranean Electrotechnical Conference (MELECON 2006)
/ - Málaga : Institute of Electrical and Electronics Engineers (IEEE), 2006, 145-148
Skup
IEEE Mediterranean Electrotechnical Conference (13 ; 2006)
Mjesto i datum
Málaga, Španjolska, 16.05.2006. - 19.05.2006
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
optimization; design of integrated circuits
Sažetak
This paper presents design and optimization procedure of a self-biased complementary folded cascade. A self biased scheme is chosen as a technique that saves power and circuit area, and is less sensitive to process variations. The gain of basic folded cascode is enhanced using a gain boosting approach based on common source self biased amplifiers. The circuits are optimized using the global optimization approach with the cost function calculated by circuit simulations. The hybrid approach to optimization is used combining the global search strategy using Particle Swarm Optimization (PSO) and Direct Pattern Search (DPS) method used as local search strategy. A complementary folded cascode operational amplifier is designed in the 0.35 μ m CMOS technology with the 3.3 V power supply voltage.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
