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Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines


Gürel, Ayla; Bogdan, Stjepan; Lewis, Frank L.; Huff, Brian
Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines // Proceedings of the 6th Mediterranean Conference on Control and Automation / Tornambe, Antonio (ur.).
Sardinija, Italija: Institute of Electrical and Electronics Engineers (IEEE), 1998. str. 125-130 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


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Naslov
Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines

Autori
Gürel, Ayla ; Bogdan, Stjepan ; Lewis, Frank L. ; Huff, Brian

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 6th Mediterranean Conference on Control and Automation / Tornambe, Antonio - : Institute of Electrical and Electronics Engineers (IEEE), 1998, 125-130

Skup
The 6th Mediterranean Conference on Control and Automation

Mjesto i datum
Sardinija, Italija, 09.06.1998. - 11.06.1998

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Sažetak
For finite-buffer manufacturing systems, the major stability issue is "deadlock", rather than "bounded-buffer-length stability." In this paper a rigorous definition of "system deadlock" is presented as a condition the absence of which throughout the system process ensures an uninterrupted flow of parts. For a very general class of finite-buffer multi-class reentrant flowline (MRF) systems, an analysis of "circular waits" yields necessary and sufficient conditions for "part- path deadlock". It is then shown that when the system contains no "key resource", "system deadlock" and "part-path deadlock" are equivalent. This allows the formulation of a one-step- look-ahead deadlock-avoidance control policy for dispatching jobs while maximizing percent utilization of resources. These results lead to a generalized kanban dispatching strategy, which is more general than the standard multi-class last buffer first serve (LBFS) dispatching strategies for finite buffer flowlines that typically under-utilize the resources. Petri net (PN) techniques are used in the analysis, using the notions of "critical siphon" and "critical trap." The problem of computational complexity associated with PN applications is overcome by using certain submatrices of the PN incidence matrix. Computationally efficient matrix techniques are given for implementing the multi-class deadlock-avoidance dispatching policy.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekti:
036011

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb


Citiraj ovu publikaciju:

Gürel, Ayla; Bogdan, Stjepan; Lewis, Frank L.; Huff, Brian
Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines // Proceedings of the 6th Mediterranean Conference on Control and Automation / Tornambe, Antonio (ur.).
Sardinija, Italija: Institute of Electrical and Electronics Engineers (IEEE), 1998. str. 125-130 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Gürel, A., Bogdan, S., Lewis, F. & Huff, B. (1998) Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines. U: Tornambe, A. (ur.)Proceedings of the 6th Mediterranean Conference on Control and Automation.
@article{article, author = {G\"{u}rel, Ayla and Bogdan, Stjepan and Lewis, Frank L. and Huff, Brian}, editor = {Tornambe, A.}, year = {1998}, pages = {125-130}, keywords = {}, title = {Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines}, keyword = {}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Sardinija, Italija} }
@article{article, author = {G\"{u}rel, Ayla and Bogdan, Stjepan and Lewis, Frank L. and Huff, Brian}, editor = {Tornambe, A.}, year = {1998}, pages = {125-130}, keywords = {}, title = {Matrix Approach To Deadlock-Free Dispatching In Multi-Class Finite Buffer Flowlines}, keyword = {}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, publisherplace = {Sardinija, Italija} }




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