Naslov
BDD complexity analysis of multiplier circuits

Autori
Grudenić, Igor ; Bogunović, Nikola

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the Joint Conferences Computers in Technical systems and Intelligent systems / Budin, Leo ; Ribarić, Slobodan - Rijeka : Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2005, 31-34

Skup
Computers in Technical Systems

Mjesto i datum
Opatija, Hrvatska, 30.05.2005. - 03.06.2005

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
formal verification; symbolic model checking; BDDs; multiplier complexity

Sažetak
The equivalence of Boolean functions is an important issue in hardware design. In order to check the equivalence of two combinatorial circuits SAT solvers and BDD based algorithms are used. For complex hardware designs efficient BDD manipulation algorithms must be employed. There is a number of industrial combinatorial circuitry for which BDD representation explodes exponentially in the number of inputs. An example of such a circuitry is multiplier that is known to have no efficient BDD representation regardless of the employed variable ordering. In this paper we analyze some important properties of the BDD representation of multipliers, as well as the complexity of the involved computations

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA