Naslov
Propagation Time Optimization Using Transistor Sizing

Autori
Butković, Željko ; Divković Pukšec, Julijana

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the 27th International Convention - MIPRO 2004, Conferences: MEET and HGS / Biljanović, Petar ; Skala, Karolj - Rijeka : Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2004, 84-88

Skup
27th International Convention - MIPRO 2004

Mjesto i datum
Hrvatska, 24.05.2004. - 28.05.2004

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
CMOS inverter; parasitic capacitances; propagation delay; PSpice

Sažetak
The CMOS inverter parasitic capacitances have been analytically estimated for the cascaded inverter pair. The optimal transistor ratio has been determined to minimize the inverter propagation delay. The chain of gradually increasing CMOS inverters have been analyzed in order to minimize the propagation delay when driving a large capacitive load. The calculation of the optimal sizing factor and the optimal number of stages of the chain has been compared for two cases: the simple one with ignoring the self-loading inverter capacitance and the more accurate that takes into account this capacitance. The PSpice analysis, based on 0.25 micron CMOS technology, has shown that the inclusion of the self-loading inverter capacitance offers better results.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika

POVEZANOST RADA