Naslov
Električka svojstva prospojnih metalnih vodova u VLSI integriranim sklopovima
(Electrical properties of VLSI interconnect)

Autori
Nenadić, Ivan

Vrsta, podvrsta i kategorija rada
Ocjenski radovi, diplomski rad

Fakultet
Fakultet elektrotehnike i računarstva

Mjesto
Zagreb

Datum
25.09

Godina
2003

Stranica
43

Mentor
Biljanović, Petar

Neposredni voditelj
Jovanović, Vladimir

Ključne riječi
VLSI; prospoji; prospajanje; metalizacija; vrijeme kašnjenja; preslušavanje; RC; RLC; prijenosne linije
(VLSI; chip; interconnect; time delay; crosstalk; RC; RLC; transmission lines)

Sažetak
The chip interconnect parasitic elemetns and their influcence on the integrated circuits were being presented in this paper. The RC, RLC and trasmission line models were also described in aspect of time delay and crosstalk analysis. A characterisitc structure was analized using FastHenry and FastCap extraction applications and the results were used to model the Spice RLC based circuit. This work also describes some methods for minimizing on-chip crosstalk and time delay and optimizing the routing of the chips interconnect.

Izvorni jezik
Hrvatski

Znanstvena područja
Elektrotehnika

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