Pregled bibliografske jedinice broj: 120250
Implementation of Sparse Matrix Arithmetic on a DSP Processor
Implementation of Sparse Matrix Arithmetic on a DSP Processor // Proceedings of the fifth IASTED International Conference on Signal and Image Processing / Hamza, M.H. (ur.).
Anaheim : Calgary : Zurich: ACTA Press, 2003. str. 93-98 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 120250 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Implementation of Sparse Matrix Arithmetic on a DSP Processor
Autori
Petrinović, Davorka ; Lukačević Ivan ; Petrinović, Davor
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings of the fifth IASTED International Conference on Signal and Image Processing
/ Hamza, M.H. - Anaheim : Calgary : Zurich : ACTA Press, 2003, 93-98
Skup
IASTED Signal and Image Processing
Mjesto i datum
Honolulu (HI), Sjedinjene Američke Države, 13.08.2003. - 15.08.2003
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
sparse matrix; random access; DSP; speech coding; LSF quantization; predictive vector quantization
Sažetak
The paper presents a method for sparse matrix multiplication on a DSP processor. Its high efficiency is a consequence of the proposed pseudo-random data memory access and parallelism of the multifunctional instructions of a DSP. Sparse matrix multiplication is implemented as linear expanded DSP code automatically generated by specially designed program. The method is applied to predictive vector quantization of Line Spectrum Frequencies vectors used in speech coding. It will be shown that the obtained reduction in computational complexity and fixed storage requirements is between two and three-fold.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
