Pregled bibliografske jedinice broj: 1169338
Particle filter implemented as a hardware accelerator in Cortex-M core periphery
Particle filter implemented as a hardware accelerator in Cortex-M core periphery // 2021 44th International Convention on Information, Communication and Electronic Technology (MIPRO)
Zagreb: Institute of Electrical and Electronics Engineers (IEEE), 2021. str. 1-6 doi:10.23919/mipro52101.2021.9596852 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
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Naslov
Particle filter implemented as a hardware
accelerator in Cortex-M core periphery
Autori
Kundrata, Jurica ; Tomic, Dubravko ; Maretic, Ivan ; Baric, Adrijan
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
2021 44th International Convention on Information, Communication and Electronic Technology (MIPRO)
/ - Zagreb : Institute of Electrical and Electronics Engineers (IEEE), 2021, 1-6
ISBN
978-953-233-101-1
Skup
44th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO 2021)
Mjesto i datum
Opatija, Hrvatska, 27.09.2021. - 01.10.2021
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
particle filters, digital integrated circuits, microprocessor core
Sažetak
Particle filters are a group of filtering methods based on recursive Bayesian filters which can be used to estimate the state of an observed dynamical system. The main advantage of the particle filters when compared to other similar filtering methods is that it can handle a nonlinear system which includes non-Gaussian noise sources. A hardware accelerator represents a digital module which is specifically made to perform some function. The module is adapted exclusively to the designed function which the module executes more efficiently and faster than it is possible using a software implementation on a generalpurpose processing core. This paper analyses a hardware accelerator which implements a particle filter used in the inertial measurement unit (IMU) measurements. The accelerator is used in periphery of a low power and low gate count Cortex-M1 core. The accelerator is evaluated with respect to the area utilization and execution performance and it is compared to a software implementation of an equivalent particle filter executed on the Cortex-M1 core. The results show that the hardware accelerator has a 30% smaller cell count than the accompanying Cortex- M1 core. The hardware implementation of the particle filter has a two-orders of magnitude shorter execution time than the reference software implementation running on the Cortex-M1 core.
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb