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Pregled bibliografske jedinice broj: 1094674

Highly parallel GPU accelerator for HEVC transform and quantization


Cobrnic, Mate; Duspara, Alen; Dragic, Leon; Piljic, Igor; Kovac, Mario
Highly parallel GPU accelerator for HEVC transform and quantization // 2020 International Conference on Image, Video Processing and Artificial Intelligence / Su, Ruidan (ur.).
Šangaj, Kina: SPIE, 2020. str. 190-195 doi:10.1117/12.2581228 (poster, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


CROSBI ID: 1094674 Za ispravke kontaktirajte CROSBI podršku putem web obrasca

Naslov
Highly parallel GPU accelerator for HEVC transform and quantization

Autori
Cobrnic, Mate ; Duspara, Alen ; Dragic, Leon ; Piljic, Igor ; Kovac, Mario

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
2020 International Conference on Image, Video Processing and Artificial Intelligence / Su, Ruidan - : SPIE, 2020, 190-195

ISBN
9781510639973

Skup
2020 International Conference on Image, Video Processing and Artificial Intelligence

Mjesto i datum
Šangaj, Kina, 21.08.2020. - 23.08.2020

Vrsta sudjelovanja
Poster

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Integer discrete cosine transform (DCT) ; High efficiency video coding (HEVC) ; Graphics processor unit (GPU) ; Matrix multiplication ; Compute unified device architecture (CUDA) ; High performance computing (HPC)

Sažetak
When analysing Internet traffic today it can be found that digital video content prevails. Its domination will continue to grow in the upcoming years and reach 82% of all traffic by 2021. If converted to Internet video minutes per second, this equals about one million video minutes per second. Providing and supporting improved compression capability is therefore expected from video processing devices. This will relieve the pressure on storage systems and communication networks while creating preconditions for further development of video services. Transform and quantization is one of the most compute-intensive parts of modern hybrid video coding systems where coding algorithm itself is commonly standardized. High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard which achieves high compression efficiency at the cost of high computational complexity. In this paper we present highly parallel GPU accelerator for HEVC transform and quantization which targets most common heterogeneous computing CPU+GPU system. The accelerator is implemented using CUDA programming model. All the relevant state-of-the-art techniques related to kernel vectorization, shared memory optimization and overlapping data transfers with computation were investigated, customized and carefully combined to obtain a performance efficient solution across all applicable transform sizes. The proposed solution is compared against reference implementation which uses NVIDIA cuBLAS library to perform the same work. Obtained speedup factors for DCI 4K frame are 2.46 times for largest transform size and 130.17 times for smallest transform size what revealed substantial performance gap of this library when targeting GPU of the Kepler architecture. Achieved processing time of frame transform and quantization are up to 4.82 ms.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo, Informacijske i komunikacijske znanosti



POVEZANOST RADA


Projekti:
EK--761349 - Prijenos tehnologije putem multinacionalnih digitalnih tehnologija specifične primjene (TETRAMAX) (Kovač, Mario; Skala, Karolj, EK ) ( CroRIS)
EK-H2020-946002 - MareNostrum experimentalna exascale računalna platforma (MEEP) (Kovač, Mario, EK ) ( CroRIS)

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Mario Kovač (autor)

Avatar Url Alen Duspara (autor)

Avatar Url Mate Čobrnić (autor)

Poveznice na cjeloviti tekst rada:

doi www.spiedigitallibrary.org

Citiraj ovu publikaciju:

Cobrnic, Mate; Duspara, Alen; Dragic, Leon; Piljic, Igor; Kovac, Mario
Highly parallel GPU accelerator for HEVC transform and quantization // 2020 International Conference on Image, Video Processing and Artificial Intelligence / Su, Ruidan (ur.).
Šangaj, Kina: SPIE, 2020. str. 190-195 doi:10.1117/12.2581228 (poster, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Cobrnic, M., Duspara, A., Dragic, L., Piljic, I. & Kovac, M. (2020) Highly parallel GPU accelerator for HEVC transform and quantization. U: Su, R. (ur.)2020 International Conference on Image, Video Processing and Artificial Intelligence doi:10.1117/12.2581228.
@article{article, author = {Cobrnic, Mate and Duspara, Alen and Dragic, Leon and Piljic, Igor and Kovac, Mario}, editor = {Su, R.}, year = {2020}, pages = {190-195}, DOI = {10.1117/12.2581228}, keywords = {Integer discrete cosine transform (DCT), High efficiency video coding (HEVC), Graphics processor unit (GPU), Matrix multiplication, Compute unified device architecture (CUDA), High performance computing (HPC)}, doi = {10.1117/12.2581228}, isbn = {9781510639973}, title = {Highly parallel GPU accelerator for HEVC transform and quantization}, keyword = {Integer discrete cosine transform (DCT), High efficiency video coding (HEVC), Graphics processor unit (GPU), Matrix multiplication, Compute unified device architecture (CUDA), High performance computing (HPC)}, publisher = {SPIE}, publisherplace = {\v{S}angaj, Kina} }
@article{article, author = {Cobrnic, Mate and Duspara, Alen and Dragic, Leon and Piljic, Igor and Kovac, Mario}, editor = {Su, R.}, year = {2020}, pages = {190-195}, DOI = {10.1117/12.2581228}, keywords = {Integer discrete cosine transform (DCT), High efficiency video coding (HEVC), Graphics processor unit (GPU), Matrix multiplication, Compute unified device architecture (CUDA), High performance computing (HPC)}, doi = {10.1117/12.2581228}, isbn = {9781510639973}, title = {Highly parallel GPU accelerator for HEVC transform and quantization}, keyword = {Integer discrete cosine transform (DCT), High efficiency video coding (HEVC), Graphics processor unit (GPU), Matrix multiplication, Compute unified device architecture (CUDA), High performance computing (HPC)}, publisher = {SPIE}, publisherplace = {\v{S}angaj, Kina} }

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