Naslov
WISHBONE Bus Interface for the No-Instruction-Set Computer (NISC)

Autori
Grubišić, Roko ; Sruk, Vlado

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of MIPRO 2009, 32nd International Convention, Vol. III., CTS & CIS / Bogunović, Nikola ; Ribarić, Slobodan - Opatija : Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2009, 71-76

ISBN
978-953-233-045-8

Skup
MIPRO 2009 32nd International Convention

Mjesto i datum
Opatija, Hrvatska, 25.05.2009. - 29.05.2009

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Wishbone; NISC; hradware accelerator; System-On-Chip

Sažetak
General-purpose processors are often unable to effectively exploit the parallelism inherent to the software code. In such cases, additional hardware accelerators are needed to enable meeting the performance goals. To shorten time to market and enable meeting design constraints, designers today use special tools and technologies like the No-Instruction-Set Computer (NISC) to automatically generate custom accelerators. However, it is often difficult to integrate these accelerators into general-purpose processor systems and use them from the main processor’ s software. In this paper we present a simple and efficient method for using the NISC processor as a loosely-coupled coprocessor. To enable communication with the NISC processor, a simple set of coprocessor services exposed to the application programmer is defined. A hardware solution based on standard SoC bus architectures for implementing these services is described. Using a standard SoC bus interface enables simple integration of the NISC design flow into an existing design flow. A practical implementation of the NISC coprocessor WISHBONE interface was realized and tested in a system based on a WISHBONE-compatible general-purpose soft processor.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA