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Pregled bibliografske jedinice broj: 358907

An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors


Shin, Dongwan; Gerstlauer, A.; Domer, R.; Gajski, Daniel D.
An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors // IEEE transactions on very large scale integration (VLSI) systems, 16 (2008), 4; 466-475 doi:10.1109/TVLSI.2007.915390 (međunarodna recenzija, članak, znanstveni)


CROSBI ID: 358907 Za ispravke kontaktirajte CROSBI podršku putem web obrasca

Naslov
An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors

Autori
Shin, Dongwan ; Gerstlauer, A. ; Domer, R. ; Gajski, Daniel D.

Izvornik
IEEE transactions on very large scale integration (VLSI) systems (1063-8210) 16 (2008), 4; 466-475

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
C language; embedded systems; high level synthesis; pipeline processing; system-on-chip

Sažetak
Much effort in register transfer level (RTL) design has been devoted to developing "push- button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo



POVEZANOST RADA


Projekti:
036-0362980-1929 - Oblikovanje okolina za ugradene sustave (Sruk, Vlado, MZO ) ( CroRIS)

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Daniel Gajski (autor)

Poveznice na cjeloviti tekst rada:

doi ieeexplore.ieee.org

Citiraj ovu publikaciju:

Shin, Dongwan; Gerstlauer, A.; Domer, R.; Gajski, Daniel D.
An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors // IEEE transactions on very large scale integration (VLSI) systems, 16 (2008), 4; 466-475 doi:10.1109/TVLSI.2007.915390 (međunarodna recenzija, članak, znanstveni)
Shin, D., Gerstlauer, A., Domer, R. & Gajski, D. (2008) An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors. IEEE transactions on very large scale integration (VLSI) systems, 16 (4), 466-475 doi:10.1109/TVLSI.2007.915390.
@article{article, author = {Shin, Dongwan and Gerstlauer, A. and Domer, R. and Gajski, Daniel D.}, year = {2008}, pages = {466-475}, DOI = {10.1109/TVLSI.2007.915390}, keywords = {C language, embedded systems, high level synthesis, pipeline processing, system-on-chip}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, doi = {10.1109/TVLSI.2007.915390}, volume = {16}, number = {4}, issn = {1063-8210}, title = {An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors}, keyword = {C language, embedded systems, high level synthesis, pipeline processing, system-on-chip} }
@article{article, author = {Shin, Dongwan and Gerstlauer, A. and Domer, R. and Gajski, Daniel D.}, year = {2008}, pages = {466-475}, DOI = {10.1109/TVLSI.2007.915390}, keywords = {C language, embedded systems, high level synthesis, pipeline processing, system-on-chip}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, doi = {10.1109/TVLSI.2007.915390}, volume = {16}, number = {4}, issn = {1063-8210}, title = {An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors}, keyword = {C language, embedded systems, high level synthesis, pipeline processing, system-on-chip} }

Časopis indeksira:


  • Current Contents Connect (CCC)
  • Web of Science Core Collection (WoSCC)
    • Science Citation Index Expanded (SCI-EXP)
    • SCI-EXP, SSCI i/ili A&HCI
  • Scopus


Citati:





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