Naslov
Interface synthesis for heterogeneous multi-core systems from transaction level models

Autori
Cho H., Abdi S., Gajski D.

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) / - , 2007, 140-142

Skup
ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Mjesto i datum
San Diego (CA), Sjedinjene Američke Države, 13.06.2007. - 15.06.2007

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Channel; Communication synthesis; HW-SW co-design; Interface synthesis; Transaction level model; Universal bridge

Sažetak
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters in the platform and generates interface modules called universal bridges between buses in the design. The design and configuration of the bridges depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the bridge can be automatically derived based on these parameters. We use industrial strength design drivers such as an MP3 decoder to test our automatically generated bridges for a variety of platforms and compare them to manually designed bridges on different quality metrics. Our experimental results show that performance of automatically generated bridges are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 5 orders of improvement in development time.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

POVEZANOST RADA