Naslov
Synthesis of System-level Bus Interfaces

Autori
Narayan, Sanjiv ; Gajski, D. D.

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Procedings of The European Design and Test Conference / - : Institute of Electrical and Electronics Engineers (IEEE), 1994, 395-399

ISBN
0-818-65411-2

Skup
The European Design and Test Conference

Mjesto i datum
Pariz, Francuska, 01.03.1994. - 03.03.1994

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
System-level Bus Architecture; Synthesis

Sažetak
Given a set of communication channels to be implemented as a single bus, the authors present a bus-generation algorithm which determines the width of a bus implementation. Tradeoffs between the width of the bus and the performance of the processes communicating over the bus are evaluated. The algorithm incorporates system level constraints such as data transfer rates and the number of pins and allows several channels that may be transferring different sizes of data to be implemented as a single bus. The authors demonstrate through a detailed example the usefulness of the algorithm in implementing system-level interfaces between modules.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo

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