Pregled bibliografske jedinice broj: 149455
VLSI Circuit Partition Using Simulated Annealing Algorithm
VLSI Circuit Partition Using Simulated Annealing Algorithm // Proceedings / MELECON 2004 / Matijašević, Maja ; Pejčinović, Branimir ; Tomšić, Željko ; Butković, Željko (ur.).
Zagreb: Institute of Electrical and Electronics Engineers (IEEE), 2004. str. 205-208 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 149455 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
VLSI Circuit Partition Using Simulated Annealing Algorithm
Autori
Kolar, Dalibor ; Divković Pukšec, Julijana ; Branica, Ivan
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
Proceedings / MELECON 2004
/ Matijašević, Maja ; Pejčinović, Branimir ; Tomšić, Željko ; Butković, Željko - Zagreb : Institute of Electrical and Electronics Engineers (IEEE), 2004, 205-208
Skup
The 12th IEEE Mediterranean Electrotechnical Conference
Mjesto i datum
Dubrovnik, Hrvatska, 12.05.2004. - 15.05.2004
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
partitioning; cost function; interconnections
Sažetak
In this work the two way partitioning of a circuit represents as a graph, was made using simulated annealing procedure. The parameters used in annealing process: initial temperature, cooling rate and the time of a process, given as a number of calculations, are chenged and its influence on the cost function (number of nets cut by partition) are described. With a proper choice of the initial temperature and the cooling rate we can obtain a good, not necessarily the best solution, not spending too much time to find out. Procedure was tested on an example with a 1000 components connected by 300 nets. We conclude that all parameters depend on a circuit itself (its size and number of interconnections).
Izvorni jezik
Engleski
Znanstvena područja
Elektrotehnika
